Modern processors employed in computer systems use various techniques to improve their performance. One of these techniques is commonly referred to as “multithreading.” Multithreading allows multiple streams of instructions, commonly referred to as “threads,” to be executed. The threads may be independent programs or related execution streams of a single parallel program or both.
Processors may support three types of multithreading. The first is commonly referred to as “coarse-grained” or “block multithreading.” Coarse-grained or block multithreading may refer to rapid switching of threads on long-latency operations. The second is commonly referred to as “fine-grained multithreading.” Fine-grained multithreading may refer to rapid switching of the threads on a cycle by cycle basis. The third type of multithreading is commonly referred to as “simultaneous multithreading.” Simultaneous multithreading may refer to scheduling of instructions from multiple threads within a single cycle.
Modern processors, such as a simultaneous multithreading (SMT) processor, may include a prefetch engine configured to prefetch data from memory, e.g., main memory, prior to the time the data is requested by the processor. The data prefetched from memory, e.g., main memory, may be speculatively prefetched based on the principle that if a memory location is addressed by the processor, the next sequential address will likely be requested by the processor in the near future. The data prefetched may be loaded in a data cache.
The location in main memory as to where to prefetch data may be determined by addresses stored in registers, commonly referred to as “prefetch registers.” These prefetch registers may also include information regarding the size and direction of the prefetched data in main memory. The size may refer to the size of the contiguous block of data to be prefetched. The direction may refer to whether the contiguous block of data is to be prefetched from main memory at the address stored in the prefetch register and upwards or is to be prefetched from main memory at the address stored in the prefetch register and downwards.
The information regarding the address, size and direction of the prefetched data may be provided in multiple instructions, referred to herein as “prefetch instructions.” One prefetch instruction may provide the address of where to prefetch the data in main memory. Another prefetch instruction may provide the size and direction. Further, these prefetch instructions may specify a particular prefetch register into which to insert the information contained in the instruction. Another prefetch instruction may indicate to the prefetch engine to prefetch the data from main memory using the information provided in a particular prefetch register.
In a multithreading processor, these prefetch instructions may be from multiple threads. If a particular prefetch instruction included information, e.g., address of the prefetched data, from a first thread, e.g., thread T0, to be stored in a particular prefetch register and another prefetch instruction included information, e.g., size and direction of the prefetched data, from a second thread, e.g., thread T1, to be stored in that same particular prefetch register, then undesirable results may occur such as prefetching the wrong data from main memory. That is, inconsistent data may be stored in a prefetch register when prefetch information from multiple threads are stored in the same prefetch register. In particular, a multithreading processor may provide for a single thread mode of operation and multithread mode operation wherein the processor switches to execute instructions from two threads, rather than safely from a single thread. The aforementioned inconsistency may arise when the mode switches because one thread may have put data into a prefetch register and the second thread could include an instruction that puts data into the same register.
Therefore, there is a need in the art to prevent at least in part inconsistent prefetch information from being stored in a prefetch register.